1. Field of the Invention
The present invention relates to electrical circuits, and, in particular, to master-slave flip-flops.
2. Description of the Related Art
A master-slave flip-flop is an electrical device that temporarily stores data, where the data is transferred into and within the device on the edges of clocking signals. The master stage of such a flip-flop stores data (received from an input stream) during one phase of a two-phase clock, and the slave stage stores data (received from the master stage) and presents that stored data as the output from the master-slave flip-flop, on the opposite phase of that clock.
FIG. 1 shows a schematic drawing of a prior-art implementation of a master-slave flip-flop 100 that relies on switched feedback techniques to retain data. Flip-flop 100 comprises inverters INV1-INV4 and switches S1-S4 arranged and operated to move data through flip-flop 100 in a particular manner. Switches S1-S4 are controlled by the levels of a two-phase clock, such that switches S1 and S4 are opened when switches S2 and S3 are closed, and vice versa. When S1 and S4 are opened and S2 and S3 are closed, the master stage receives a data signal from input node D. When S1 and S4 are closed and S2 and S3 are opened, data stored in the master stage is passed to the slave stage. When S1 and S4 are opened again and S2 and S3 are closed again, the data received by the slave stage from the master stage is stored in the slave stage, while the master stage receives a new data signal from node D. In this way, master-slave flip-flop 100 temporarily stores data received from an input data stream.
Flip-flops such as flip-flop 100 of FIG. 1 have certain disadvantages. In particular, the most basic design requires four switches and four inverters, which utilize layout area as well as power.
FIG. 2 shows a schematic drawing of a prior-art implementation of a master-slave flip-flop 200 that relies on weak feedback techniques to retain data. In flip-flop 200, inverters INV2 and INV4 are weak inverters that are designed to have a very small drive. As such, INV2 and INV4 are almost negligible under normal operating conditions, but will provide enough positive feedback during standby (i.e., when switches S1 and S2, respectively, are opened) to retain information in the flip-flop. Since INV2 and INV4 have very small drives, flip-flop 200 can be designed without switches (such as S2 and S4 of FIG. 1) in the feedback paths of the master and slave stages, since the input signals received at nodes I4 and I1 from nodes I2 and D, respectively, will be sufficiently large to control the state of inverters INV1 and INV3, no matter what signals are received from weak inverters INV2 and INV4, respectively.
Flip-flop 200 has certain advantages over flip-flop 100 of FIG. 1. First of all, flip-flop 200 has two fewer switches than flip-flop 100. Moreover, flip-flop 200 replaces two of the strong inverters of flip-flop 100 with two weak inverters. As such, flip-flop 200 has a smaller layout area and lower power dissipation than flip-flop 100.
Flip-flop 200 is not without problems, however. One important problem with flip-flop 200 relates to data shoot-through. As with flip-flop 100, switches S1 and S2 of flip-flop 200 are typically controlled by a two-phase clock. Since S1 and S2 need to be out of phase with one another (i.e., S1 is opened when S2 is closed, and vice versa), one standard technique is to use a received clock signal CK and an inverted version of the received clock signal (CKX) to control the states of the switches. In a simple implementation, the inverted clock signal CKX is generated by inverting the received clock signal CK using a standard inverter gate.
Because the inverter gate used to generate the inverted clock signal CKX is not an infinitely fast device, there will be a delay between the time when the received clock signal CK changes from one state to another (e.g., from low to high) and the time when the inverted clock signal CKX changes from one state to another (e.g., from high to low). During this delay period, depending upon the previous phase of the flip-flop, switches S1 and S2 may be either both opened or both closed for a short period of time. When switches S1 and S2 are both temporarily opened, there is no adverse impact to the operation of the flip-flop. However, when switches S1 and S2 are both temporarily closed, there is a possibility that the data received by the master stage will prematurely shoot through into the slave stage, thereby potentially corrupting the data generated at the output node Q.
This data shoot-through problem can be solved by adding relatively sophisticated circuitry to control very precisely the states of switches S1 and S2 to avoid the situation where switches S1 and S2 are both closed for too long a period of time. Such sophisticated circuitry adds to, rather than subtracts from, both layout area and power requirements. Moreover, such circuitry can adversely affect the speed of the flip-flop (i.e., slow it down).